Memory devices consume static power because of leakage through its transistors. To counter the leakage problem, low leakage (high dielectric constant) transistors and circuit techniques have been used.
FIG. 1 shows a prior art register file 100. The local bit line (LBL) 1 140 is a distributed domino (typically 8:1) multiplexer and is connected to several adjacent one bit cells 110 and 120 in LBL block 1 101. The LBL 1 140 can be merged with LBL 2 145 using a two input AND NOT (NAND) gate 185. The output of the NAND gate 185 is sent to a global bit line 182 that merges many LBLs along a memory column.
The access of the one bit cells 110 and 120 are controlled by read word line (RdWL). During the pre-charge phase of the LBLs 140 and 145, pre-charge devices 160 and 170 pull up the voltage level of the LBLs 140 and 145 respectively. The voltage level of the LBLs 140 and 145 is typically pulled up to the voltage supply VCC 190 of the register file 100. When register file 100 is inactive, the RdWL of each one bit cell 110 and 120 deactivates transistors 112 and 122 respectively and the data stored in each one bit cell 110 and 120 cannot be accessed by the LBLs 140 and 145.
Static power consumption of the register file 100 can occur through the leakage of transistors 112 and 122. For example, when LBL 1 140 is pre-charged to VCC, when the transistors 112 and 122 are deactivated by the RdWLs of the one bit cells 110 and 120 respectively, and when the transistors 114 and 124 are activated by the data stored in the one bit cells 110 and 120 respectively, leakage via transistors 112 and 122 can occur. This is because the drain and source terminal of transistors 112 and 122 are at VCC and at ground potential respectively.
FIG. 2 shows a prior art register file 200 with a transistor 210 added to reduce the leakage of the LBL 140. The source terminal of transistors 114 and 124 are connected to the drain terminal of transistor 210. Capacitors 212 and 214 represent the equivalent capacitance seen by LBL 1 140 and LBL 2 145 respectively. When register file 200 is inactive, transistor 210 is deactivated to reduce the leakage of transistors 112 and 122. Unlike the earlier example where the source terminal of transistors 112 and 122 are at ground potential, a deactivated transistor 210 can provide leakage reduction by disconnecting the path of the source terminal of transistors 112 and 122 to the ground terminal.
However, the circuit technique used in register file 200 has several flaws. The transistor 210 weakens the pull-down network of the one bit cells 110 and 120 since the charge on the capacitor 212 has to go through transistor 210. To compensate for the delay caused by the weakening of the pull-down network, transistor 210 is typically made three times larger than the typical transistor in register file 200. A virtual VSS track 211 is also required to connect transistors 114 and 124 to transistor 210. In addition, the increase in size of transistor 210 to compensate the delay can also cause the leakage of transistor 210 to increase and it offsets the leakage reduction of transistors 112 and 122.